Research Cell: An International Journal of Engineering Sciences

Kuldeep Singh Sidhu ¹, Ashwani Kumar Singla ¹

Affiliations
1 ECE Section, Yadavindra College of Engineering, Talwandi Sabo, IN

Abstract

This paper proposes the implementation of a low power and high speed Vedic Divider based on ancient Indian Vedic mathematics. In this paper, an algorithm based on the "ParavartyaYojayet" is applied, throughout this sutra the propagation delay and power consumption are reduced to an extent. As considered, division operation is more complex in the computation of the digital applications. The most significant aspect of thispaper is to reducethe power consumption and provide high speed. In this work decimal and binary number division algorithms are performed. Synthesis results are calculated on Tanner EDA Tool 13.0 at 32nm technology. The simulated results for proposedVedic divider shows a reduction in delay and power consumption against other division methods.

Keywords

Paravartya Sutra, Vedic Divider, Binary Division.

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Ikwinder Singh Maan ¹, Ashwani Kumar Singla ¹

Affiliations
1 ECE Department, Yadavindra College of Engineering, Talwandi Sabo, IN

Abstract

The SQRT Carry Select Adder (CSA) architectures using parallel prefix adder instead of Ripple Carry Adders (RCA) are implemented and analyzed in this paper. Brent Kung (BK) parallel prefix structure uses to designed a Square Root Carry-Select Adder (SQRT CSA) at different word size and reduced area and power dissipation as compared to that of conventional SQRT CSA. Ripple Carry Adder (RCA) takes longer computation time and Carry Look-ahead scheme (CLA) used to derive fast results but they increase in area and, the carry complexity increases by increasing the width of the adder for the higher bit. Carry Select Adder is a best compromise between RCA and CLA in term of area and delay. The architecture of 16-bit BK SQRT CSA is configured into five different stages and it extends up to 32-bit. Power, delay, PDP and Transistor count of 16 bit adder architectures are calculated at different stage level at 1.0v input voltage. The architecture has been synthesized at 32nm technology at 1.0v using Tanner EDA tool 13.0v. The simulations of Modified SQRT BKA CSA are performed in T-Spice. The results depict that Modified BKA SQRT CSA is better than all the other adder architectures in terms of power, delay and area.

Keywords

Parallel Prefix Adder(PPA), Modified Square Root Brent Kung Adder Carry Select adder (SQRT BKA CSA), Binary-to-excess-1 converter (BEC), etc.

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